® An Introduction to the Intel QuickPath Interconnect

January 2009 Document Number: 320412-001US Notice: This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information. Legal Lines and Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. 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Copyright © 2009, Intel Corporation. All Rights Reserved. 2 ® An Introduction to the Intel QuickPath Interconnect Contents Executive Overview ..............................................................................................................5 Introduction ........................................................................................................................5 Paper Scope and Organization ...............................................................................................6 Evolution of Processor Interface .............................................................................................6 Interconnect Overview ..........................................................................................................8 Interconnect Details ............................................................................................................10 Physical Layer ................................................................................................................... 10 Link Layer ......................................................................................................................... 12 Routing Layer .................................................................................................................... 14 Transport Layer ................................................................................................................. 14 Protocol Layer ................................................................................................................... 15 Performance ...................................................................................................................... 19 Reliability, Availability, and Serviceability ............................................................................... 21 Processor Bus Applications .................................................................................................. 21 Summary .......................................................................................................................... 22 ® An Introduction to the Intel QuickPath Interconnect 3 Revision History Document Number 320412 Revision Number -001US Initial Release Description § Date January 2009 4 ® An Introduction to the Intel QuickPath Interconnect Executive Overview ® Intel microprocessors advance their performance ascension through ongoing microarchitecture evolutions and multi-core proliferation. The processor interconnect has similarly evolved (see Figure 1), thereby keeping pace with microprocessor needs through faster buses, quad-pumped buses, dual